Dual D-type flip-flop with set and reset; positive-edge trigger；EM74LVC74A

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EM74LVC74A

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Number of channels	2
Technology family	LVC
Supply voltage (min) (V)	1.65
Supply voltage (max) (V)	3.6
Input type	Standard CMOS
Output type	Push-Pull
Clock frequency (max) (MHz)	100
IOL (max) (mA)	24
IOH (max) (mA)	-24
Supply current (max) (µA)	10
Features	Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)
Operating temperature range (°C)	-40 to 125
Rating	Catalog

EM74LVC74AD	LVC74A XYYWW	SOP-14L	plastic small outline package; 14 leads; body width 3.9 mm
EM74LVC74APW	LVC74A XYYWW	TSSOP-14L	plastic thin shrink small outline package; 14 leads; body width 4.4 mm

Wide supply voltage range from 1.2 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options

The EM74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nS D) and (nR D) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to HIGH clock transition, for predictable operation.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.