Inverter with open-drain output-EM74LVC1G06

Home Products Logic LVC series Inverter with open-drain output-EM74LVC1G06

EM74LVC1G06

Inverter with open-drain output-EM74LVC1G06

Product Details
Design and Development
Support and Training

Product details

Technology family	LVC
Supply voltage (min) (V)	1.65
Supply voltage (max) (V)	5.5
Number of channels	1
IOL (max) (mA)	32
IOH (max) (mA)	0
Supply current (max) (µA)	4
Input type	Standard CMOS
Output type	Open-drain
Features	Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Rating	Catalog
Operating temperature range (°C)	-40 to 125

EM74LVC1G06GV	SOT23-5L	SOT23 package, 5 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height	123456	12345689
EM74LVC1G06GW	SOT353	SOT353 package, 5 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height	123456	12345689
EM74LVC1G06GS	DFN1x1-6L	DFN1×1 package, 6 pins 1 mm × 1 mm; 0.4 mm (Max) height	123456	12345689
EM74LVC1G06GM	DFN1x1.45-6L	DFN1.45×1 package, 6 pins 1.45 mm × 1 mm; 0.6 mm (Max) height	123456	12345689
EM74LVC1G06GX	DFN0.8x0.8-4L	DFN0.8×0.8 package, 5pins 0.8 mm × 0.8 mm; 0.4 mm (Max) height	123456	12345689

Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 100 mA
Direct interface with TTL levels
Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V
• MM JESD22-A115C Class C exceeds 550 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options

The EM74LVC1G06 is a single inverter with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.