8-bit dual supply translating transceiver; 3-state

Home Products Logic LVC series 8-bit dual supply translating transceiver; 3-state | EM74LVC8T245; EM74LVCH8T245

EM74LVC8T245; EM74LVCH8T245

8-bit dual supply translating transceiver; 3-state | EM74LVC8T245; EM74LVCH8T245

Product Details
Design and Development
Support and Training

Product details

EM74LVC8T245PW	LVC8T245 XYYWW	TSSOP-24L	plastic thin shrink small outline package; 24 leads;body width 4.4 mm
EM74LVCH8T245PW	LVCH8T245 XYYWW	TSSOP-24L	plastic thin shrink small outline package; 24 leads;body width 4.4 mm

Wide supply voltage range
• VCC(A): 1.2 V to 5.5 V
• VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
Suspend mode
Latch-up performance exceeds 250 mA
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 30 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2500 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Maximum data rates:
• 420 Mbps (3.3 V to 5.0 V translation)
• 200 Mbps (translate to 3.3 V)
• 140 Mbps (translate to 2.5 V)
• 75 Mbps (translate to 1.8 V)
• 50 Mbps (translate to 1.5 V)
Multiple package options

The EM74LVC8T245; EM74LVCH8T245 is an 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the EM74LVCH8T245 holds unused or floating data inputs at a valid logic level.