Single buffer-EM74LVC1G16

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EM74LVC1G16

Single buffer-EM74LVC1G16

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Product details

Technology family	LVC
Supply voltage (min) (V)	1.65
Supply voltage (max) (V)	5.5
Number of channels	1
IOL (max) (mA)	32
Supply current (max) (µA)	4
IOH (max) (mA)	-32
Input type	Schmitt-Trigger
Operating temperature range (°C)	-40 to 125

EM74LVC1G16GV	SOT23-5L	SOT23 package, 5 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height
EM74LVC1G16GW	SOT353	SOT353 package, 5 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height
EM74LVC1G16GS	DFN1x1-6L	DFN1×1 package, 6 pins 1 mm × 1 mm; 0.42 mm (Max) height
EM74LVC1G16GM	DFN1x1.45-6L	DFN1.45×1 package, 6 pins 1.45 mm × 1 mm; 0.6 mm (Max) height
EM74LVC1G16GX	DFN0.8x0.8-4L	DFN0.8×0.8 package, 5pins 0.8 mm × 0.8 mm; 0.4 mm (Max) height

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
CMOS low power dissipation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 100 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V
• MM JESD22-A115C Class C exceeds 550 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options

The EM74LVC1G16 provides a low-power, low-voltage single buffer. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.