Low-power configurable multiple function gate-EM74LVC1G57

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EM74LVC1G57

Low-power configurable multiple function gate-EM74LVC1G57

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Product details

Technology family	LVC
Supply voltage (min) (V)	1.65
Supply voltage (max) (V)	5.5
Number of channels	1
Inputs per channel	1
IOL (max) (mA)	32
IOH (max) (mA)	-32
Input type	Schmitt-Trigger
Output type	Push-Pull
Features	Over-voltage tolerant inputs, High noise immunity, CMOS low power dissipation
Rating	Catalog
Operating temperature range (°C)	-40 to 125

EM74LVC1G57GV	SOT23-6L	SOT23 package, 6 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height
EM74LVC1G57GW	SOT363	SOT363 package, 6 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height

Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Latch-up performance exceeds 100 mA
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options

The EM74LVC1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.